From b84e75626ae78558b8f526a276e4597c5ca6c429 Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Tue, 2 Jun 2026 15:36:58 -0700 Subject: [PATCH 1/6] ARL: Release v1.19 event files This commit releases ARL v1.19 events and updates mapfile.csv accordingly. --- ARL/events/arrowlake_crestmont_core.json | 861 +++++++++++++++--- ARL/events/arrowlake_lioncove_core.json | 126 +-- ARL/events/arrowlake_skymont_core.json | 8 +- ARL/events/arrowlake_uncore.json | 6 +- ARL/events/arrowlake_uncore_experimental.json | 6 +- mapfile.csv | 18 +- 6 files changed, 823 insertions(+), 202 deletions(-) diff --git a/ARL/events/arrowlake_crestmont_core.json b/ARL/events/arrowlake_crestmont_core.json index 1648dac4..9a0875dd 100644 --- a/ARL/events/arrowlake_crestmont_core.json +++ b/ARL/events/arrowlake_crestmont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17", - "DatePublished": "02/26/2026", - "Version": "1.17", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19", + "DatePublished": "04/17/2026", + "Version": "1.19", "Legend": "" }, "Events": [ @@ -304,6 +304,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x05", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.WCB_FULL", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x05", "UMask": "0x81", @@ -331,6 +358,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x05", + "UMask": "0x82", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.WCB_FULL_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x05", "UMask": "0x84", @@ -1006,6 +1060,60 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x30", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "L2_REJECT_XQ.ANY", + "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.", + "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x31", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "CORE_REJECT_L2Q.ANY", + "BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.", + "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x34", "UMask": "0x01", @@ -1825,7 +1933,439 @@ "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.ALL_P", + "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", + "PublicDescription": "Counts the number of retirement slots not consumed due to backend stalls", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "SERIALIZATION.NON_C01_MS_SCB", + "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.", + "PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "SERIALIZATION.C01_MS_SCB", + "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.", + "PublicDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "SERIALIZATION.COLOR_STALLS", + "BriefDescription": "Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.", + "PublicDescription": "Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "ICACHE.MISSES", + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "ICACHE.ACCESSES", + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -1844,12 +2384,12 @@ "Speculative": "1" }, { - "EventCode": "0x73", + "EventCode": "0x85", "UMask": "0x01", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", + "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "PublicDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -1871,15 +2411,15 @@ "Speculative": "1" }, { - "EventCode": "0x73", + "EventCode": "0x85", "UMask": "0x02", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "SampleAfterValue": "2000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -1898,15 +2438,15 @@ "Speculative": "1" }, { - "EventCode": "0x73", - "UMask": "0x03", + "EventCode": "0x85", + "UMask": "0x04", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "SampleAfterValue": "2000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -1925,15 +2465,15 @@ "Speculative": "1" }, { - "EventCode": "0x73", - "UMask": "0x04", + "EventCode": "0x85", + "UMask": "0x0e", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "SampleAfterValue": "200003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -1952,15 +2492,15 @@ "Speculative": "1" }, { - "EventCode": "0x74", - "UMask": "0x00", + "EventCode": "0x85", + "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BE_BOUND.ALL_P", - "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", - "PublicDescription": "Counts the number of retirement slots not consumed due to backend stalls", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.", + "PublicDescription": "Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "SampleAfterValue": "200003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -1979,15 +2519,15 @@ "Speculative": "1" }, { - "EventCode": "0x74", - "UMask": "0x01", + "EventCode": "0x85", + "UMask": "0x20", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "PublicDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", + "SampleAfterValue": "2000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2006,12 +2546,12 @@ "Speculative": "1" }, { - "EventCode": "0x74", - "UMask": "0x02", + "EventCode": "0xb2", + "UMask": "0x01", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.", + "EventName": "FP_VINT_UOPS_EXECUTED.STD", + "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.", + "PublicDescription": "Counts the number of uops executed on floating point and vector integer store data port.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -2033,12 +2573,12 @@ "Speculative": "1" }, { - "EventCode": "0x74", - "UMask": "0x08", + "EventCode": "0xb2", + "UMask": "0x02", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )", + "EventName": "FP_VINT_UOPS_EXECUTED.P0", + "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.", + "PublicDescription": "Counts the number of uops executed on floating point and vector integer port 0.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -2060,12 +2600,12 @@ "Speculative": "1" }, { - "EventCode": "0x74", - "UMask": "0x10", + "EventCode": "0xb2", + "UMask": "0x04", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "EventName": "FP_VINT_UOPS_EXECUTED.P1", + "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.", + "PublicDescription": "Counts the number of uops executed on floating point and vector integer port 1.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -2087,12 +2627,12 @@ "Speculative": "1" }, { - "EventCode": "0x74", - "UMask": "0x20", + "EventCode": "0xb2", + "UMask": "0x08", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BE_BOUND.REGISTER", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).", + "EventName": "FP_VINT_UOPS_EXECUTED.P2", + "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.", + "PublicDescription": "Counts the number of uops executed on floating point and vector integer port 2.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -2114,12 +2654,12 @@ "Speculative": "1" }, { - "EventCode": "0x74", - "UMask": "0x40", + "EventCode": "0xb2", + "UMask": "0x0e", "UMaskExt": "0x00", - "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", - "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY", + "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2.", + "PublicDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -2141,15 +2681,15 @@ "Speculative": "1" }, { - "EventCode": "0x75", - "UMask": "0x04", + "EventCode": "0xb2", + "UMask": "0x0f", "UMaskExt": "0x00", - "EventName": "SERIALIZATION.C01_MS_SCB", - "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.", - "PublicDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.", + "EventName": "FP_VINT_UOPS_EXECUTED.ALL", + "BriefDescription": "Counts the number of uops executed on all floating point ports.", + "PublicDescription": "Counts the number of uops executed on all floating point ports.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "200003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2168,15 +2708,15 @@ "Speculative": "1" }, { - "EventCode": "0x80", - "UMask": "0x02", + "EventCode": "0xb3", + "UMask": "0x01", "UMaskExt": "0x00", - "EventName": "ICACHE.MISSES", - "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", - "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "EventName": "INT_UOPS_EXECUTED.LD", + "BriefDescription": "Counts the number of uops executed on a load port.", + "PublicDescription": "Counts the number of uops executed on a load port. This event counts for integer uops even if the destination is FP/vector", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "200003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2195,15 +2735,15 @@ "Speculative": "1" }, { - "EventCode": "0x80", - "UMask": "0x03", + "EventCode": "0xb3", + "UMask": "0x02", "UMaskExt": "0x00", - "EventName": "ICACHE.ACCESSES", - "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", - "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "EventName": "INT_UOPS_EXECUTED.STA", + "BriefDescription": "Counts the number of uops executed on a Store address port.", + "PublicDescription": "Counts the number of uops executed on a Store address port. This event counts integer uops even if the data source is FP/vector", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "200003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2222,12 +2762,12 @@ "Speculative": "1" }, { - "EventCode": "0x85", - "UMask": "0x01", + "EventCode": "0xb3", + "UMask": "0x04", "UMaskExt": "0x00", - "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", - "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", - "PublicDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "EventName": "INT_UOPS_EXECUTED.STD_JMP", + "BriefDescription": "Counts the number of uops executed on an integer store data and jump port.", + "PublicDescription": "Counts the number of uops executed on an integer store data and jump port.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -2249,15 +2789,15 @@ "Speculative": "1" }, { - "EventCode": "0x85", - "UMask": "0x02", + "EventCode": "0xb3", + "UMask": "0x08", "UMaskExt": "0x00", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.", - "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "EventName": "INT_UOPS_EXECUTED.P0", + "BriefDescription": "Counts the number of uops executed on integer port 0.", + "PublicDescription": "Counts the number of uops executed on integer port 0.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2276,15 +2816,15 @@ "Speculative": "1" }, { - "EventCode": "0x85", - "UMask": "0x04", + "EventCode": "0xb3", + "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.", - "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", + "EventName": "INT_UOPS_EXECUTED.P1", + "BriefDescription": "Counts the number of uops executed on integer port 1.", + "PublicDescription": "Counts the number of uops executed on integer port 1.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2303,15 +2843,15 @@ "Speculative": "1" }, { - "EventCode": "0x85", - "UMask": "0x0e", + "EventCode": "0xb3", + "UMask": "0x20", "UMaskExt": "0x00", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", - "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "EventName": "INT_UOPS_EXECUTED.P2", + "BriefDescription": "Counts the number of uops executed on integer port 2.", + "PublicDescription": "Counts the number of uops executed on integer port 2.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "200003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2330,15 +2870,15 @@ "Speculative": "1" }, { - "EventCode": "0x85", - "UMask": "0x10", + "EventCode": "0xb3", + "UMask": "0x40", "UMaskExt": "0x00", - "EventName": "ITLB_MISSES.WALK_PENDING", - "BriefDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.", - "PublicDescription": "Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks.", + "EventName": "INT_UOPS_EXECUTED.P3", + "BriefDescription": "Counts the number of uops executed on integer port 3.", + "PublicDescription": "Counts the number of uops executed on integer port 3.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "200003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2357,15 +2897,15 @@ "Speculative": "1" }, { - "EventCode": "0x85", - "UMask": "0x20", + "EventCode": "0xb3", + "UMask": "0x78", "UMaskExt": "0x00", - "EventName": "ITLB_MISSES.STLB_HIT", - "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", - "PublicDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "EventName": "INT_UOPS_EXECUTED.PRIMARY", + "BriefDescription": "Counts the number of uops executed on integer port 0,1, 2, 3.", + "PublicDescription": "Counts the number of uops executed on integer port 0,1, 2, 3.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", + "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", @@ -2384,12 +2924,12 @@ "Speculative": "1" }, { - "EventCode": "0xb2", - "UMask": "0x01", + "EventCode": "0xb3", + "UMask": "0xff", "UMaskExt": "0x00", - "EventName": "FP_VINT_UOPS_EXECUTED.STD", - "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.", - "PublicDescription": "Counts the number of uops executed on floating point and vector integer store data port.", + "EventName": "INT_UOPS_EXECUTED.ALL", + "BriefDescription": "Counts the number of uops executed on all Integer ports.", + "PublicDescription": "Counts the number of uops executed on all Integer ports.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -2707,6 +3247,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0xc3", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.FAST", + "BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.", + "PublicDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0xc3", "UMask": "0x20", @@ -2734,6 +3301,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0xc3", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP", + "BriefDescription": "Counts the number of virtual traps taken.", + "PublicDescription": "Counts the number of virtual traps taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0xc3", "UMask": "0x6f", @@ -4489,6 +5083,33 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xd0", + "UMask": "0x83", + "UMaskExt": "0x00", + "EventName": "MEM_UOPS_RETIRED.ALL", + "BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)", + "PublicDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xd1", "UMask": "0x01", diff --git a/ARL/events/arrowlake_lioncove_core.json b/ARL/events/arrowlake_lioncove_core.json index d4deaa82..e87f180d 100644 --- a/ARL/events/arrowlake_lioncove_core.json +++ b/ARL/events/arrowlake_lioncove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17", - "DatePublished": "02/26/2026", - "Version": "1.17", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19", + "DatePublished": "04/17/2026", + "Version": "1.19", "Legend": "" }, "Events": [ @@ -5436,11 +5436,11 @@ }, { "EventCode": "0xc4", - "UMask": "0x01", + "UMask": "0x00", "UMaskExt": "0x01", - "EventName": "BR_INST_RETIRED.COND_TAKEN", - "BriefDescription": "Taken conditional branch instructions retired.", - "PublicDescription": "Counts taken conditional branch instructions retired.", + "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", + "BriefDescription": "Taken forward conditional branch instructions retired.", + "PublicDescription": "Counts taken forward conditional branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", @@ -5464,10 +5464,10 @@ { "EventCode": "0xc4", "UMask": "0x01", - "UMaskExt": "0x00", - "EventName": "BR_INST_RETIRED.COND_TAKEN_BWD", - "BriefDescription": "Taken backward conditional branch instructions retired.", - "PublicDescription": "Counts taken backward conditional branch instructions retired.", + "UMaskExt": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", @@ -5490,14 +5490,14 @@ }, { "EventCode": "0xc4", - "UMask": "0x02", + "UMask": "0x01", "UMaskExt": "0x00", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "BriefDescription": "Direct and indirect near call instructions retired.", - "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "EventName": "BR_INST_RETIRED.COND_TAKEN_BWD", + "BriefDescription": "Taken backward conditional branch instructions retired.", + "PublicDescription": "Counts taken backward conditional branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "100007", + "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -5518,13 +5518,13 @@ { "EventCode": "0xc4", "UMask": "0x02", - "UMaskExt": "0x01", - "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", - "BriefDescription": "Taken forward conditional branch instructions retired.", - "PublicDescription": "Counts taken forward conditional branch instructions retired.", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "400009", + "SampleAfterValue": "100007", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -5814,18 +5814,18 @@ }, { "EventCode": "0xc5", - "UMask": "0x01", - "UMaskExt": "0x80", - "EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST", - "BriefDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", - "PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", - "CollectPEBSRecord": "3", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -5841,14 +5841,14 @@ }, { "EventCode": "0xc5", - "UMask": "0x02", + "UMask": "0x08", "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", - "BriefDescription": "Mispredicted indirect CALL retired.", - "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "EventName": "BR_MISP_RETIRED.RET", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired.", + "PublicDescription": "This event counts the number of mispredicted ret instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "400009", + "SampleAfterValue": "100007", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -5868,18 +5868,18 @@ }, { "EventCode": "0xc5", - "UMask": "0x02", - "UMaskExt": "0x80", - "EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST", - "BriefDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", - "PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", - "CollectPEBSRecord": "3", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -5895,14 +5895,14 @@ }, { "EventCode": "0xc5", - "UMask": "0x08", - "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.RET", - "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", - "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "UMask": "0x11", + "UMaskExt": "0x01", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "100007", + "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -5922,11 +5922,11 @@ }, { "EventCode": "0xc5", - "UMask": "0x10", + "UMask": "0x20", "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.COND_NTAKEN", - "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", - "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", @@ -5949,18 +5949,18 @@ }, { "EventCode": "0xc5", - "UMask": "0x11", + "UMask": "0x40", "UMaskExt": "0x01", - "EventName": "BR_MISP_RETIRED.COND", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -5976,18 +5976,18 @@ }, { "EventCode": "0xc5", - "UMask": "0x20", - "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", - "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "UMask": "0x41", + "UMaskExt": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", + "BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -6004,10 +6004,10 @@ { "EventCode": "0xc5", "UMask": "0x41", - "UMaskExt": "0x01", - "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", - "BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", - "PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", diff --git a/ARL/events/arrowlake_skymont_core.json b/ARL/events/arrowlake_skymont_core.json index 2335be34..d704bb15 100644 --- a/ARL/events/arrowlake_skymont_core.json +++ b/ARL/events/arrowlake_skymont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17", - "DatePublished": "02/26/2026", - "Version": "1.17", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19", + "DatePublished": "04/17/2026", + "Version": "1.19", "Legend": "" }, "Events": [ @@ -1740,7 +1740,7 @@ "UMask": "0x00", "UMaskExt": "0x00", "EventName": "CORE_REJECT_L2Q.ANY", - "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.", + "BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.", "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", diff --git a/ARL/events/arrowlake_uncore.json b/ARL/events/arrowlake_uncore.json index 25d1829b..05a86136 100644 --- a/ARL/events/arrowlake_uncore.json +++ b/ARL/events/arrowlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17", - "DatePublished": "02/26/2026", - "Version": "1.17", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19", + "DatePublished": "04/17/2026", + "Version": "1.19", "Legend": "" }, "Events": [ diff --git a/ARL/events/arrowlake_uncore_experimental.json b/ARL/events/arrowlake_uncore_experimental.json index 30ab1836..916b2e68 100644 --- a/ARL/events/arrowlake_uncore_experimental.json +++ b/ARL/events/arrowlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.17", - "DatePublished": "02/26/2026", - "Version": "1.17", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.19", + "DatePublished": "04/17/2026", + "Version": "1.19", "Legend": "" }, "Events": [ diff --git a/mapfile.csv b/mapfile.csv index 8ad43854..42bf830d 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -223,16 +223,16 @@ GenuineIntel-6-BD,V1.22,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40 GenuineIntel-6-BD,V1.22,/LNL/events/lunarlake_uncore.json,uncore,,, GenuineIntel-6-BD,V1.22,/LNL/events/lunarlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-BD,V1.1,/LNL/metrics/lunarlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-C5,V1.17,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-C5,V1.17,/ARL/events/arrowlake_crestmont_core.json,hybridcore,0x20,0x000002,LowPower_Atom -GenuineIntel-6-C5,V1.17,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-C5,V1.17,/ARL/events/arrowlake_uncore.json,uncore,,, -GenuineIntel-6-C5,V1.17,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-C5,V1.19,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-C5,V1.19,/ARL/events/arrowlake_crestmont_core.json,hybridcore,0x20,0x000002,LowPower_Atom +GenuineIntel-6-C5,V1.19,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-C5,V1.19,/ARL/events/arrowlake_uncore.json,uncore,,, +GenuineIntel-6-C5,V1.19,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-C5,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-C6,V1.17,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-C6,V1.17,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-C6,V1.17,/ARL/events/arrowlake_uncore.json,uncore,,, -GenuineIntel-6-C6,V1.17,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-C6,V1.19,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-C6,V1.19,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-C6,V1.19,/ARL/events/arrowlake_uncore.json,uncore,,, +GenuineIntel-6-C6,V1.19,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-C6,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core GenuineIntel-6-CC,V1.05,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom GenuineIntel-6-CC,V1.05,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core From 3f1d40d1953193e75c6b5a559638cf1f67bacaed Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Tue, 2 Jun 2026 15:36:59 -0700 Subject: [PATCH 2/6] EMR: Release v1.24 event files This commit releases EMR v1.24 events and updates mapfile.csv accordingly. --- EMR/events/emeraldrapids_core.json | 31 +++++++++++++++++-- EMR/events/emeraldrapids_uncore.json | 6 ++-- .../emeraldrapids_uncore_experimental.json | 6 ++-- mapfile.csv | 6 ++-- 4 files changed, 37 insertions(+), 12 deletions(-) diff --git a/EMR/events/emeraldrapids_core.json b/EMR/events/emeraldrapids_core.json index 52d81a55..a80199b6 100644 --- a/EMR/events/emeraldrapids_core.json +++ b/EMR/events/emeraldrapids_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.23", - "DatePublished": "02/20/2026", - "Version": "1.23", + "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.24", + "DatePublished": "05/19/2026", + "Version": "1.24", "Legend": "" }, "Events": [ @@ -2232,6 +2232,31 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x42", + "UMask": "0x02", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "BriefDescription": "Cycles when L1D is locked", + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x43", "UMask": "0xfd", diff --git a/EMR/events/emeraldrapids_uncore.json b/EMR/events/emeraldrapids_uncore.json index fe2be9c0..0848627c 100644 --- a/EMR/events/emeraldrapids_uncore.json +++ b/EMR/events/emeraldrapids_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.23", - "DatePublished": "02/20/2026", - "Version": "1.23", + "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.24", + "DatePublished": "05/19/2026", + "Version": "1.24", "Legend": "" }, "Events": [ diff --git a/EMR/events/emeraldrapids_uncore_experimental.json b/EMR/events/emeraldrapids_uncore_experimental.json index 9e5ef4a4..f0fbbf18 100644 --- a/EMR/events/emeraldrapids_uncore_experimental.json +++ b/EMR/events/emeraldrapids_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.23", - "DatePublished": "02/20/2026", - "Version": "1.23", + "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.24", + "DatePublished": "05/19/2026", + "Version": "1.24", "Legend": "" }, "Events": [ diff --git a/mapfile.csv b/mapfile.csv index 42bf830d..83794689 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -143,9 +143,9 @@ GenuineIntel-6-8F,V1.39,/SPR/events/sapphirerapids_core.json,core,,, GenuineIntel-6-8F,V1.39,/SPR/events/sapphirerapids_uncore.json,uncore,,, GenuineIntel-6-8F,V1.39,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-8F,V1.2,/SPR/metrics/sapphirerapids_metrics.json,metrics,,, -GenuineIntel-6-CF,V1.23,/EMR/events/emeraldrapids_core.json,core,,, -GenuineIntel-6-CF,V1.23,/EMR/events/emeraldrapids_uncore.json,uncore,,, -GenuineIntel-6-CF,V1.23,/EMR/events/emeraldrapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-CF,V1.24,/EMR/events/emeraldrapids_core.json,core,,, +GenuineIntel-6-CF,V1.24,/EMR/events/emeraldrapids_uncore.json,uncore,,, +GenuineIntel-6-CF,V1.24,/EMR/events/emeraldrapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-CF,V1.2,/EMR/metrics/emeraldrapids_metrics.json,metrics,,, GenuineIntel-6-6A,V1.30,/ICX/events/icelakex_core.json,core,,, GenuineIntel-6-6A,V1.30,/ICX/events/icelakex_uncore.json,uncore,,, From 875354c88686ef50387d9601f52354a6da8f24cc Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Tue, 2 Jun 2026 15:36:59 -0700 Subject: [PATCH 3/6] GNR: Release v1.19 event files This commit releases GNR v1.19 events and updates mapfile.csv accordingly. --- GNR/events/graniterapids_core.json | 6 ++--- GNR/events/graniterapids_uncore.json | 8 +++---- .../graniterapids_uncore_experimental.json | 24 ++++++++++++++++--- mapfile.csv | 12 +++++----- 4 files changed, 34 insertions(+), 16 deletions(-) diff --git a/GNR/events/graniterapids_core.json b/GNR/events/graniterapids_core.json index 1a3a9ceb..2a8fcdd7 100644 --- a/GNR/events/graniterapids_core.json +++ b/GNR/events/graniterapids_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.18", - "DatePublished": "04/09/2026", - "Version": "1.18", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.19", + "DatePublished": "04/23/2026", + "Version": "1.19", "Legend": "" }, "Events": [ diff --git a/GNR/events/graniterapids_uncore.json b/GNR/events/graniterapids_uncore.json index 1e319702..421089c3 100644 --- a/GNR/events/graniterapids_uncore.json +++ b/GNR/events/graniterapids_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.18", - "DatePublished": "04/09/2026", - "Version": "1.18", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.19", + "DatePublished": "04/23/2026", + "Version": "1.19", "Legend": "" }, "Events": [ @@ -4029,7 +4029,7 @@ "FCMask": "0x00", "UMaskExt": "0x00000000", "EventName": "UNC_M_PRE_COUNT.PGT", - "BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.", + "BriefDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel.", "PublicDescription": "DRAM Precharge commands.", "Counter": "0,1,2,3", "ELLC": "0", diff --git a/GNR/events/graniterapids_uncore_experimental.json b/GNR/events/graniterapids_uncore_experimental.json index a719db06..11996ada 100644 --- a/GNR/events/graniterapids_uncore_experimental.json +++ b/GNR/events/graniterapids_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.18", - "DatePublished": "04/09/2026", - "Version": "1.18", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.19", + "DatePublished": "04/23/2026", + "Version": "1.19", "Legend": "" }, "Events": [ @@ -4093,6 +4093,24 @@ "FILTER_VALUE": "0", "CounterType": "PGMABLE" }, + { + "Unit": "IRP", + "EventCode": "0x1E", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, { "Unit": "UPI LL", "EventCode": "0x02", diff --git a/mapfile.csv b/mapfile.csv index 83794689..877a6b29 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -200,14 +200,14 @@ GenuineIntel-6-B5,V1.21,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore, GenuineIntel-6-B5,V1.21,/MTL/events/meteorlake_uncore.json,uncore,,, GenuineIntel-6-B5,V1.21,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-B5,V1.1,/MTL/metrics/meteorlake_metrics_redwoodcove_core.json,metrics,0x40,0x000002,Core -GenuineIntel-6-AD,V1.18,/GNR/events/graniterapids_core.json,core,,, -GenuineIntel-6-AD,V1.18,/GNR/events/graniterapids_uncore.json,uncore,,, -GenuineIntel-6-AD,V1.18,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AD,V1.19,/GNR/events/graniterapids_core.json,core,,, +GenuineIntel-6-AD,V1.19,/GNR/events/graniterapids_uncore.json,uncore,,, +GenuineIntel-6-AD,V1.19,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AD,V1.2,/GNR/metrics/graniterapids_metrics.json,metrics,,, GenuineIntel-6-AD,V1.08,/GNR/metrics/graniterapids_retire_latency.json,retire latency,,, -GenuineIntel-6-AE,V1.18,/GNR/events/graniterapids_core.json,core,,, -GenuineIntel-6-AE,V1.18,/GNR/events/graniterapids_uncore.json,uncore,,, -GenuineIntel-6-AE,V1.18,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AE,V1.19,/GNR/events/graniterapids_core.json,core,,, +GenuineIntel-6-AE,V1.19,/GNR/events/graniterapids_uncore.json,uncore,,, +GenuineIntel-6-AE,V1.19,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AE,V1.2,/GNR/metrics/graniterapids_metrics.json,metrics,,, GenuineIntel-6-AE,V1.08,/GNR/metrics/graniterapids_retire_latency.json,retire latency,,, GenuineIntel-6-AF,V1.17,/SRF/events/sierraforest_core.json,core,,, From 5535a3e8cc14ae8ef58013cf3d8e9480018b911a Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Tue, 2 Jun 2026 15:37:00 -0700 Subject: [PATCH 4/6] LNL: Release v1.25 event files This commit releases LNL v1.25 events and updates mapfile.csv accordingly. --- LNL/events/lunarlake_lioncove_core.json | 126 +++++------ LNL/events/lunarlake_skymont_core.json | 62 +++++- LNL/events/lunarlake_uncore.json | 82 ++++++- LNL/events/lunarlake_uncore_experimental.json | 202 +++++++++++++++++- mapfile.csv | 8 +- 5 files changed, 399 insertions(+), 81 deletions(-) diff --git a/LNL/events/lunarlake_lioncove_core.json b/LNL/events/lunarlake_lioncove_core.json index 60bf42fe..55b4bf6d 100644 --- a/LNL/events/lunarlake_lioncove_core.json +++ b/LNL/events/lunarlake_lioncove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.22", - "DatePublished": "02/26/2026", - "Version": "1.22", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.25", + "DatePublished": "05/05/2026", + "Version": "1.25", "Legend": "" }, "Events": [ @@ -5463,11 +5463,11 @@ }, { "EventCode": "0xc4", - "UMask": "0x01", + "UMask": "0x00", "UMaskExt": "0x01", - "EventName": "BR_INST_RETIRED.COND_TAKEN", - "BriefDescription": "Taken conditional branch instructions retired.", - "PublicDescription": "Counts taken conditional branch instructions retired.", + "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", + "BriefDescription": "Taken forward conditional branch instructions retired.", + "PublicDescription": "Counts taken forward conditional branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", @@ -5491,10 +5491,10 @@ { "EventCode": "0xc4", "UMask": "0x01", - "UMaskExt": "0x00", - "EventName": "BR_INST_RETIRED.COND_TAKEN_BWD", - "BriefDescription": "Taken backward conditional branch instructions retired.", - "PublicDescription": "Counts taken backward conditional branch instructions retired.", + "UMaskExt": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", @@ -5517,14 +5517,14 @@ }, { "EventCode": "0xc4", - "UMask": "0x02", + "UMask": "0x01", "UMaskExt": "0x00", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "BriefDescription": "Direct and indirect near call instructions retired.", - "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "EventName": "BR_INST_RETIRED.COND_TAKEN_BWD", + "BriefDescription": "Taken backward conditional branch instructions retired.", + "PublicDescription": "Counts taken backward conditional branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "100007", + "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -5545,13 +5545,13 @@ { "EventCode": "0xc4", "UMask": "0x02", - "UMaskExt": "0x01", - "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", - "BriefDescription": "Taken forward conditional branch instructions retired.", - "PublicDescription": "Counts taken forward conditional branch instructions retired.", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "400009", + "SampleAfterValue": "100007", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -5841,18 +5841,18 @@ }, { "EventCode": "0xc5", - "UMask": "0x01", - "UMaskExt": "0x80", - "EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST", - "BriefDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", - "PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", - "CollectPEBSRecord": "3", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -5868,14 +5868,14 @@ }, { "EventCode": "0xc5", - "UMask": "0x02", + "UMask": "0x08", "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", - "BriefDescription": "Mispredicted indirect CALL retired.", - "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "EventName": "BR_MISP_RETIRED.RET", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired.", + "PublicDescription": "This event counts the number of mispredicted ret instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "400009", + "SampleAfterValue": "100007", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -5895,18 +5895,18 @@ }, { "EventCode": "0xc5", - "UMask": "0x02", - "UMaskExt": "0x80", - "EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST", - "BriefDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", - "PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", - "CollectPEBSRecord": "3", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -5922,14 +5922,14 @@ }, { "EventCode": "0xc5", - "UMask": "0x08", - "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.RET", - "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", - "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "UMask": "0x11", + "UMaskExt": "0x01", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", - "SampleAfterValue": "100007", + "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -5949,11 +5949,11 @@ }, { "EventCode": "0xc5", - "UMask": "0x10", + "UMask": "0x20", "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.COND_NTAKEN", - "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", - "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", @@ -5976,18 +5976,18 @@ }, { "EventCode": "0xc5", - "UMask": "0x11", + "UMask": "0x40", "UMaskExt": "0x01", - "EventName": "BR_MISP_RETIRED.COND", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -6003,18 +6003,18 @@ }, { "EventCode": "0xc5", - "UMask": "0x20", - "UMaskExt": "0x00", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", - "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "UMask": "0x41", + "UMaskExt": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", + "BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "0", "CounterMask": "0", "Invert": "0", @@ -6031,10 +6031,10 @@ { "EventCode": "0xc5", "UMask": "0x41", - "UMaskExt": "0x01", - "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", - "BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", - "PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "400009", diff --git a/LNL/events/lunarlake_skymont_core.json b/LNL/events/lunarlake_skymont_core.json index ee829d3f..dcdfd45b 100644 --- a/LNL/events/lunarlake_skymont_core.json +++ b/LNL/events/lunarlake_skymont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.22", - "DatePublished": "02/26/2026", - "Version": "1.22", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.25", + "DatePublished": "05/05/2026", + "Version": "1.25", "Legend": "" }, "Events": [ @@ -1794,7 +1794,7 @@ "UMask": "0x00", "UMaskExt": "0x00", "EventName": "CORE_REJECT_L2Q.ANY", - "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.", + "BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.", "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", @@ -5191,6 +5191,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0xc3", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP", + "BriefDescription": "Counts number of virtual trap actually taken (e.g. highest priority event during retirement). It can count virtual trap from FPC port 0 or port 1 (x87/SSE) equally in a single counter.", + "PublicDescription": "Counts number of virtual trap actually taken (e.g. highest priority event during retirement). It can count virtual trap from FPC port 0 or port 1 (x87/SSE) equally in a single counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0xc3", "UMask": "0x6e", @@ -5407,6 +5434,33 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.TAKEN", + "BriefDescription": "Counts the number of taken branch instructions retired", + "PublicDescription": "Counts the number of taken branch instructions retired", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xc4", "UMask": "0xbf", diff --git a/LNL/events/lunarlake_uncore.json b/LNL/events/lunarlake_uncore.json index cca0828e..b1bf84b0 100644 --- a/LNL/events/lunarlake_uncore.json +++ b/LNL/events/lunarlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.22", - "DatePublished": "02/26/2026", - "Version": "1.22", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.25", + "DatePublished": "05/05/2026", + "Version": "1.25", "Legend": "" }, "Events": [ @@ -13,7 +13,7 @@ "UMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M_CAS_COUNT_RD", - "BriefDescription": "Read CAS command sent to DRAM", + "BriefDescription": "Read CAS command sent to DRAM.", "PublicDescription": "Read CAS command sent to DRAM", "Counter": "0,1,2,3,4", "Deprecated": "0", @@ -25,12 +25,60 @@ "UMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M_CAS_COUNT_WR", - "BriefDescription": "Write CAS command sent to DRAM", + "BriefDescription": "Write CAS command sent to DRAM.", "PublicDescription": "Write CAS command sent to DRAM", "Counter": "0,1,2,3,4", "Deprecated": "0", "CounterType": "PGMABLE" }, + { + "Unit": "iMC", + "EventCode": "0x24", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_ACT_COUNT_RD", + "BriefDescription": "ACT command for a read request sent to DRAM.", + "PublicDescription": "ACT command for a read request sent to DRAM", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x25", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_ACT_COUNT_WR", + "BriefDescription": "ACT command for a write request sent to DRAM.", + "PublicDescription": "ACT command for a write request sent to DRAM", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x26", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_ACT_COUNT_TOTAL", + "BriefDescription": "ACT command sent to DRAM.", + "PublicDescription": "ACT command sent to DRAM", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x27", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", + "BriefDescription": "PRE command sent to DRAM for a read/write request.", + "PublicDescription": "PRE command sent to DRAM for a read/write request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, { "Unit": "iMC", "EventCode": "0x3C", @@ -43,6 +91,30 @@ "Deprecated": "0", "CounterType": "PGMABLE" }, + { + "Unit": "iMC", + "EventCode": "0x3B", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_WR_DATA", + "BriefDescription": "Counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data.", + "PublicDescription": "Counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data.", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x3A", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RD_DATA", + "BriefDescription": "Counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.", + "PublicDescription": "This counter counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, { "Unit": "SANTA", "EventCode": "0x00", diff --git a/LNL/events/lunarlake_uncore_experimental.json b/LNL/events/lunarlake_uncore_experimental.json index c6aeaf7a..52e2660b 100644 --- a/LNL/events/lunarlake_uncore_experimental.json +++ b/LNL/events/lunarlake_uncore_experimental.json @@ -1,19 +1,115 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.22", - "DatePublished": "02/26/2026", - "Version": "1.22", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.25", + "DatePublished": "05/05/2026", + "Version": "1.25", "Legend": "" }, "Events": [ + { + "Unit": "iMC", + "EventCode": "0x01", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "Counting the number of clocks.", + "PublicDescription": "Counting the number of clocks.", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_VC0_REQUESTS_RD", + "BriefDescription": "Incoming VC0 read request.", + "PublicDescription": "Incoming VC0 read request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_VC0_REQUESTS_WR", + "BriefDescription": "Incoming VC0 write request.", + "PublicDescription": "Incoming VC0 write request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x04", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_VC1_REQUESTS_RD", + "BriefDescription": "Incoming VC1 read request.", + "PublicDescription": "Incoming VC1 read request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x05", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_VC1_REQUESTS_WR", + "BriefDescription": "Incoming VC1 write request.", + "PublicDescription": "Incoming VC1 write request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x12", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_SELF_REFRESH", + "BriefDescription": "DRAM in Self-refresh (all channels).", + "PublicDescription": "DRAM in Self-refresh (all channels)", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x13", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RD_OCCUPANCY_CH0", + "BriefDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch).", + "PublicDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch)", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x14", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RD_OCCUPANCY_CH1", + "BriefDescription": "Number of VC0 read in channel1 - this event can increment by more than 1 (per channel/sub-ch).", + "PublicDescription": "Number of VC0 read in channel1 - this event can increment by more than 1 (per channel/sub-ch)", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, { "Unit": "iMC", "EventCode": "0x19", "UMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M_DRAM_THERMAL_HOT", - "BriefDescription": "Any Rank at Hot state", + "BriefDescription": "Any Rank at Hot state.", "PublicDescription": "Any Rank at Hot state", "Counter": "0,1,2,3,4", "Deprecated": "0", @@ -25,11 +121,107 @@ "UMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M_DRAM_THERMAL_WARM", - "BriefDescription": "Any Rank at Warm state", + "BriefDescription": "Any Rank at Warm state.", "PublicDescription": "Any Rank at Warm state", "Counter": "0,1,2,3,4", "Deprecated": "0", "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1C", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_HIT_RD", + "BriefDescription": "Incoming read request page status is Page Hit.", + "PublicDescription": "incoming read request page status is Page Hit", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1D", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", + "BriefDescription": "Incoming read request page status is Page Empty.", + "PublicDescription": "incoming read request page status is Page Empty", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1E", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_MISS_RD", + "BriefDescription": "Incoming read request page status is Page Miss.", + "PublicDescription": "incoming read request page status is Page Miss", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1F", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_HIT_WR", + "BriefDescription": "Incoming write request page status is Page Hit.", + "PublicDescription": "incoming write request page status is Page Hit", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x20", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", + "BriefDescription": "Incoming write request page status is Page Empty.", + "PublicDescription": "incoming write request page status is Page Empty", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x21", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_MISS_WR", + "BriefDescription": "Incoming write request page status is Page Miss.", + "PublicDescription": "incoming write request page status is Page Miss", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x29", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_CKE_OFF_CYCLES", + "BriefDescription": "CKE in DRAM is low.", + "PublicDescription": "CKE in DRAM is low", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x39", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TOTAL_REQUESTS", + "BriefDescription": "Total number of requests entering MC, this is the sum of all RD + WR requests for all VCs.", + "PublicDescription": "Total number of requests entering MC, this is the sum of all RD + WR requests for all VCs", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" } ] } \ No newline at end of file diff --git a/mapfile.csv b/mapfile.csv index 877a6b29..615ef061 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -218,10 +218,10 @@ GenuineIntel-6-B6,V1.12,/GRR/events/grandridge_core.json,core,,, GenuineIntel-6-B6,V1.12,/GRR/events/grandridge_uncore.json,uncore,,, GenuineIntel-6-B6,V1.12,/GRR/events/grandridge_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-B6,V1.02,/GRR/metrics/grandridge_metrics.json,metrics,,, -GenuineIntel-6-BD,V1.22,/LNL/events/lunarlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-BD,V1.22,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-BD,V1.22,/LNL/events/lunarlake_uncore.json,uncore,,, -GenuineIntel-6-BD,V1.22,/LNL/events/lunarlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BD,V1.25,/LNL/events/lunarlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-BD,V1.25,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-BD,V1.25,/LNL/events/lunarlake_uncore.json,uncore,,, +GenuineIntel-6-BD,V1.25,/LNL/events/lunarlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-BD,V1.1,/LNL/metrics/lunarlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core GenuineIntel-6-C5,V1.19,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom GenuineIntel-6-C5,V1.19,/ARL/events/arrowlake_crestmont_core.json,hybridcore,0x20,0x000002,LowPower_Atom From ffc03fc3b414127c5a36bbb648e500c4afeff134 Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Tue, 2 Jun 2026 15:37:00 -0700 Subject: [PATCH 5/6] PTL: Release v1.06 event files This commit releases PTL v1.06 events and updates mapfile.csv accordingly. --- PTL/events/pantherlake_cougarcove_core.json | 10 +- PTL/events/pantherlake_darkmont_core.json | 68 +++++- PTL/events/pantherlake_uncore.json | 94 +++++++- .../pantherlake_uncore_experimental.json | 227 ++++++++++++++++++ mapfile.csv | 12 +- 5 files changed, 388 insertions(+), 23 deletions(-) create mode 100644 PTL/events/pantherlake_uncore_experimental.json diff --git a/PTL/events/pantherlake_cougarcove_core.json b/PTL/events/pantherlake_cougarcove_core.json index 5f946e29..34e6d5de 100644 --- a/PTL/events/pantherlake_cougarcove_core.json +++ b/PTL/events/pantherlake_cougarcove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.05", - "DatePublished": "02/26/2026", - "Version": "1.05", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.06", + "DatePublished": "05/06/2026", + "Version": "1.06", "Legend": "" }, "Events": [ @@ -6546,8 +6546,8 @@ "UMask": "0x08", "UMaskExt": "0x00", "EventName": "BR_MISP_RETIRED.NEAR_RETURN", - "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS [This event is alias to BR_MISP_RETIRED.RET]", - "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. [This event is alias to BR_MISP_RETIRED.RET]", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired [This event is alias to BR_MISP_RETIRED.RET]", + "PublicDescription": "This event counts the number of mispredicted ret instructions retired [This event is alias to BR_MISP_RETIRED.RET]", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", "SampleAfterValue": "100007", diff --git a/PTL/events/pantherlake_darkmont_core.json b/PTL/events/pantherlake_darkmont_core.json index 156bd07e..b17a6ffb 100644 --- a/PTL/events/pantherlake_darkmont_core.json +++ b/PTL/events/pantherlake_darkmont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.05", - "DatePublished": "02/26/2026", - "Version": "1.05", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.06", + "DatePublished": "05/06/2026", + "Version": "1.06", "Legend": "" }, "Events": [ @@ -2496,8 +2496,8 @@ "UMask": "0x08", "UMaskExt": "0x00", "EventName": "SERIALIZATION.COLOR_STALLS", - "BriefDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.", - "PublicDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.", + "BriefDescription": "Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.", + "PublicDescription": "Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -3900,8 +3900,8 @@ "UMask": "0x10", "UMaskExt": "0x00", "EventName": "MACHINE_CLEARS.MRN_NUKE", - "BriefDescription": "Counts the number of machines clears due to memory renaming.", - "PublicDescription": "Counts the number of machines clears due to memory renaming.", + "BriefDescription": "Counts the number of machine clears due to memory renaming.", + "PublicDescription": "Counts the number of machine clears due to memory renaming.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -4759,6 +4759,60 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0xc5", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.NEAR_RET", + "BriefDescription": "This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "BR_MISP_RETIRED.NEAR_RETURN", + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired. [This event is alias to BR_MISP_RETIRED.NEAR_RET]", + "PublicDescription": "Counts the number of mispredicted near RET branch instructions retired. [This event is alias to BR_MISP_RETIRED.NEAR_RET]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xc5", "UMask": "0x50", diff --git a/PTL/events/pantherlake_uncore.json b/PTL/events/pantherlake_uncore.json index c9615375..2f46f00a 100644 --- a/PTL/events/pantherlake_uncore.json +++ b/PTL/events/pantherlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.05", - "DatePublished": "02/26/2026", - "Version": "1.05", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.06", + "DatePublished": "05/06/2026", + "Version": "1.06", "Legend": "" }, "Events": [ @@ -13,7 +13,7 @@ "UMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M_CAS_COUNT_RD", - "BriefDescription": "Read CAS command sent to DRAM", + "BriefDescription": "Read CAS command sent to DRAM.", "PublicDescription": "Read CAS command sent to DRAM", "Counter": "0,1,2,3,4", "Deprecated": "0", @@ -25,12 +25,60 @@ "UMask": "0x00", "UMaskExt": "0x00", "EventName": "UNC_M_CAS_COUNT_WR", - "BriefDescription": "Write CAS command sent to DRAM", + "BriefDescription": "Write CAS command sent to DRAM.", "PublicDescription": "Write CAS command sent to DRAM", "Counter": "0,1,2,3,4", "Deprecated": "0", "CounterType": "PGMABLE" }, + { + "Unit": "iMC", + "EventCode": "0x24", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_ACT_COUNT_RD", + "BriefDescription": "ACT command for a read request sent to DRAM.", + "PublicDescription": "ACT command for a read request sent to DRAM", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x25", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_ACT_COUNT_WR", + "BriefDescription": "ACT command for a write request sent to DRAM.", + "PublicDescription": "ACT command for a write request sent to DRAM", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x26", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_ACT_COUNT_TOTAL", + "BriefDescription": "ACT command sent to DRAM.", + "PublicDescription": "ACT command sent to DRAM", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x27", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", + "BriefDescription": "PRE command sent to DRAM for a read/write request.", + "PublicDescription": "PRE command sent to DRAM for a read/write request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, { "Unit": "iMC", "EventCode": "0x3C", @@ -42,6 +90,42 @@ "Counter": "0,1,2,3,4", "Deprecated": "0", "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x3B", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_WR_DATA", + "BriefDescription": "Counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data.", + "PublicDescription": "Counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data.", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x3A", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RD_DATA", + "BriefDescription": "Counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.", + "PublicDescription": "Counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "SANTA", + "EventCode": "0x00", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UNC_CLOCK.SOCKET", + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "Counter": "FIXED", + "Deprecated": "0", + "CounterType": "FIXED" } ] } \ No newline at end of file diff --git a/PTL/events/pantherlake_uncore_experimental.json b/PTL/events/pantherlake_uncore_experimental.json new file mode 100644 index 00000000..ce3d5367 --- /dev/null +++ b/PTL/events/pantherlake_uncore_experimental.json @@ -0,0 +1,227 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.06", + "DatePublished": "05/06/2026", + "Version": "1.06", + "Legend": "" + }, + "Events": [ + { + "Unit": "iMC", + "EventCode": "0x01", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "Counting the number of clocks.", + "PublicDescription": "Counting the number of clocks.", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_VC0_REQUESTS_RD", + "BriefDescription": "Incoming VC0 read request.", + "PublicDescription": "Incoming VC0 read request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_VC0_REQUESTS_WR", + "BriefDescription": "Incoming VC0 write request.", + "PublicDescription": "Incoming VC0 write request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x04", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_VC1_REQUESTS_RD", + "BriefDescription": "Incoming VC1 read request.", + "PublicDescription": "Incoming VC1 read request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x05", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_VC1_REQUESTS_WR", + "BriefDescription": "Incoming VC1 write request.", + "PublicDescription": "Incoming VC1 write request", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x12", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_SELF_REFRESH", + "BriefDescription": "DRAM in Self-refresh (all channels).", + "PublicDescription": "DRAM in Self-refresh (all channels)", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x13", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RD_OCCUPANCY_CH0", + "BriefDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch).", + "PublicDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch)", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x14", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RD_OCCUPANCY_CH1", + "BriefDescription": "Number of VC0 read in channel1 - this event can increment by more than 1 (per channel/sub-ch).", + "PublicDescription": "Number of VC0 read in channel1 - this event can increment by more than 1 (per channel/sub-ch)", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x19", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_THERMAL_HOT", + "BriefDescription": "Any Rank at Hot state.", + "PublicDescription": "Any Rank at Hot state", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1A", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_THERMAL_WARM", + "BriefDescription": "Any Rank at Warm state.", + "PublicDescription": "Any Rank at Warm state", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1C", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_HIT_RD", + "BriefDescription": "Incoming read request page status is Page Hit.", + "PublicDescription": "incoming read request page status is Page Hit", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1D", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", + "BriefDescription": "Incoming read request page status is Page Empty.", + "PublicDescription": "incoming read request page status is Page Empty", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1E", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_MISS_RD", + "BriefDescription": "Incoming read request page status is Page Miss.", + "PublicDescription": "incoming read request page status is Page Miss", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x1F", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_HIT_WR", + "BriefDescription": "Incoming write request page status is Page Hit.", + "PublicDescription": "incoming write request page status is Page Hit", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x20", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", + "BriefDescription": "Incoming write request page status is Page Empty.", + "PublicDescription": "incoming write request page status is Page Empty", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x21", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_PAGE_MISS_WR", + "BriefDescription": "Incoming write request page status is Page Miss.", + "PublicDescription": "incoming write request page status is Page Miss", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x29", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_CKE_OFF_CYCLES", + "BriefDescription": "CKE in DRAM is low.", + "PublicDescription": "CKE in DRAM is low", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x39", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TOTAL_REQUESTS", + "BriefDescription": "Total number of requests entering MC, this is the sum of all RD + WR requests for all VCs.", + "PublicDescription": "Total number of requests entering MC, this is the sum of all RD + WR requests for all VCs", + "Counter": "0,1,2,3,4", + "Deprecated": "0", + "CounterType": "PGMABLE" + } + ] +} \ No newline at end of file diff --git a/mapfile.csv b/mapfile.csv index 615ef061..e1304787 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -234,12 +234,12 @@ GenuineIntel-6-C6,V1.19,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40 GenuineIntel-6-C6,V1.19,/ARL/events/arrowlake_uncore.json,uncore,,, GenuineIntel-6-C6,V1.19,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-C6,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-CC,V1.05,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom -GenuineIntel-6-CC,V1.05,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core -GenuineIntel-6-CC,V1.05,/PTL/events/pantherlake_uncore.json,uncore,,, -GenuineIntel-6-D5,V1.05,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom -GenuineIntel-6-D5,V1.05,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core -GenuineIntel-6-D5,V1.05,/PTL/events/pantherlake_uncore.json,uncore,,, +GenuineIntel-6-CC,V1.06,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom +GenuineIntel-6-CC,V1.06,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core +GenuineIntel-6-CC,V1.06,/PTL/events/pantherlake_uncore.json,uncore,,, +GenuineIntel-6-D5,V1.06,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom +GenuineIntel-6-D5,V1.06,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core +GenuineIntel-6-D5,V1.06,/PTL/events/pantherlake_uncore.json,uncore,,, GenuineIntel-6-DD,V1.02,/CWF/events/clearwaterforest_core.json,core,,, GenuineIntel-6-DD,V1.02,/CWF/events/clearwaterforest_uncore.json,uncore,,, GenuineIntel-6-DD,V1.02,/CWF/events/clearwaterforest_uncore_experimental.json,uncore experimental,,, From 9d614951b7fe3577c2bb8fb5fc73ef4c6f14a96c Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Tue, 2 Jun 2026 15:56:40 -0700 Subject: [PATCH 6/6] mapfile: Add PTL experimental uncore references Update PTL mapfile entries to also link the experimental uncore event file. --- mapfile.csv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mapfile.csv b/mapfile.csv index e1304787..8af82f92 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -237,9 +237,11 @@ GenuineIntel-6-C6,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics GenuineIntel-6-CC,V1.06,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom GenuineIntel-6-CC,V1.06,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core GenuineIntel-6-CC,V1.06,/PTL/events/pantherlake_uncore.json,uncore,,, +GenuineIntel-6-CC,V1.06,/PTL/events/pantherlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-D5,V1.06,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom GenuineIntel-6-D5,V1.06,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core GenuineIntel-6-D5,V1.06,/PTL/events/pantherlake_uncore.json,uncore,,, +GenuineIntel-6-D5,V1.06,/PTL/events/pantherlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-DD,V1.02,/CWF/events/clearwaterforest_core.json,core,,, GenuineIntel-6-DD,V1.02,/CWF/events/clearwaterforest_uncore.json,uncore,,, GenuineIntel-6-DD,V1.02,/CWF/events/clearwaterforest_uncore_experimental.json,uncore experimental,,,