arm: hisilicon: add hi3516av100 SoC support (CRG + DT + higmac driver)#44
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… Kconfig) V2A generation (Cortex-A7, ARMv7) SoC family — Hi3516AV100 and the pin-compatible Hi3516DV100. Same shape as the V2 cv200 / 3518ev20x support landed in #43 except this one is ARMv7 with GIC + arch-timer instead of VIC + SP804. Adds: - drivers/clk/hisilicon/crg-hi3516av100.c (~330 lines): ported from the 4.9 vendor BSP clk-hi3516a.c onto the modern crg- platform_ driver scaffold (mirroring crg-hi3516cv200.c). - 34 fixed-rate roots (3 / 6 / 13.5 / 24 / 25 / 27 / 37.125 / 50 / 74.25 / 75 / 99 / 100 / 125 / 145 / 148.5 / 150 / 194 / 198 / 200 / 229 / 237 / 242 / 250 / 297 / 300 / 333 / 400 / 500 / 594 / 600 / 750 / 900 / 1000 / 1188 MHz) - APLL stub fixed-rate at 850 MHz (mid of vendor OPP table) — full PLL programming is a follow-up; the kernel boots fine with the U-Boot-configured CPU rate. - 9 muxes (sysaxi, snor, snand, nand, mmc0/1, uart, eth_phy, a7) - 1 fixed-factor (clk_sysapb = sysaxi_mux / 4) - 15 gates (snor/snand/nand, mmc0/1, usb utmi/hrst, uart0-3, eth + eth_macif, spi0-1, dmac) - CLK_OF_DECLARE early init for sysctrl timer slots (8 entries — av100 exposes TIME0_0..TIME3_7 vs cv200's 4) and early UART / ETH consumers needing clk_get during start_kernel before platform_driver probing. - Noop reset-controller with 2-cell xlate so higmac probe doesn't defer forever waiting for resets. - arch/arm/boot/dts/hisilicon/hi3516av100.dtsi (~290 lines): - GIC v2 at 0x20300000 (cortex-a7-gic). - Architected ARM generic timer (arm,armv7-timer) — av100 has Cortex-A7 generic timer; SP804 dual_timer is exposed but disabled by default and only board files can enable. - PL011 uart0-3, PL022 spi0/1, PL061 gpio0-3 (vendor BSP wires 16 GPIO chips; mainline port enables 4 — sufficient for a DEMB board; rest can be added per-board). - hisi-i2c-hisilicon i2c_bus0-2, hisi-spi-nor controller. - higmac ethernet at 0x10090000 with MDIO sub-node — distinct from cv200/cv300's femac. - himci mmc0/1 at 0x206e0000/0x206f0000. - Skeleton.dtsi removed (4.18+ convention; explicit #address-cells/#size-cells on root). - arch/arm/boot/dts/hisilicon/hi3516av100-demb.dts (~95 lines): Reference board — 1 GiB RAM at 0x80000000, single Cortex-A7 Linux CPU (vendor BSP layout, even though the SoC has 2 cores), UART0 console at 115200n8, higmac + MDIO ethphy@1 rgmii. - include/dt-bindings/clock/hi3516av100-clock.h: clock IDs. - arch/arm/mach-hibvt/Kconfig: ARCH_HI3516AV100 entry. depends on ARCH_MULTI_V7. selects HAVE_ARM_ARCH_TIMER, ARM_GIC, COMMON_CLK_HI3516AV100, ARCH_HAS_RESET_CONTROLLER. Note: does NOT select ARM_TIMER_SP804 because arch-timer is preferred on this SoC (Cortex-A7 generic timer). - drivers/clk/hisilicon/Kconfig: COMMON_CLK_HI3516AV100 entry. - drivers/clk/hisilicon/Makefile: register the new object. - arch/arm/boot/dts/hisilicon/Makefile: register the demb.dtb. After this patch, the kernel boots end-to-end on an av100 board. Real hardware verification is gated on the openhisilicon-side OSAL shim work (#170 expanded the V2A blob-symbol set) and on a separate firmware-side av100_neo defconfig — neither block landing this kernel-side support. Co-authored-by: Vasiliy Yakovlev <vixand@openipc.org> Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Minimal mainline platform driver for the higmac (Gigabit Ethernet MAC)
IP block used on Hi3516AV100 / Hi3516DV100. The vendor 4.9 BSP carries
a 3000-line driver in drivers/net/ethernet/hisilicon/higmac/ with TSO,
EEE, AVS, multicast filters, statistics, ethtool, PM, etc. This port
strips everything except the descriptor-ring TX/RX path that QEMU
emulates and that real hardware needs to boot — sufficient for ifup,
DHCP, and ping; production features can be layered on later.
Register layout follows the QEMU machine model
(qemu-hisilicon hw/net/hisi-gmac.c) which mirrors the vendor IP:
0x0000 STATION_ADDR_LOW MAC address
0x0004 STATION_ADDR_HIGH
0x0040 PORT_MODE 100M full hardcoded for QEMU
0x0044 PORT_EN bit1 RX_EN | bit2 TX_EN
0x0064 REC_FILT_CONTROL permissive (BIT_CRC_ERR_PASS)
0x03C0 MDIO_SINGLE_CMD embedded mii_bus
0x03C4 MDIO_SINGLE_DATA
0x0500 RX_FQ_* (free queue) SW pushes empty buffers
0x0520 RX_BQ_* (buffer queue) HW pushes received frames
0x0580 TX_BQ_* (send queue) SW pushes outgoing
0x05A0 TX_RQ_* (reclaim queue) HW pushes completions
0x05C0 RAW_PMU_INT IRQ status (W1C)
0x05C4 ENA_PMU_INT IRQ mask
0x05CC DESC_WR_RD_ENA master DMA enable (0xF = all on)
Driver structure mirrors hisi_femac.c — platform_driver, single
NAPI instance (weight 64), devm clk/reset acquisition,
of_phy_get_and_connect via embedded mdio sub-node, dma_alloc_coherent
ring memory. MDIO is at offset 0x3c0 of the same MMIO region as the
MAC (vendor used a separate hisilicon,hisi-gemac-mdio platform device
for this; mainline registers the mii_bus inline since the MMIO range
is contiguous).
DT bindings:
reg — single MAC MMIO range
interrupts — combined IRQ
clocks/clock-names — "higmac_clk" + "macif_clk" (both optional)
resets/reset-names — "port_reset" + "macif_reset" (both optional)
phy-handle — reference to mdio child's PHY node
phy-mode — "rgmii" / "mii" / "rmii"
mac-address — from DT or random fallback
DTSI delta: drops the separate hisilicon,hisi-gemac-mdio node and
folds an mdio sub-node into the higmac itself; the demb.dts moves the
ethphy@1 into that sub-node. Matches the mainline-friendly layout for
GMAC + MDIO sharing one MMIO range.
Out of scope (vendor driver has, mainline port doesn't):
- TSO / GSO / GRO (NAPI uses napi_gro_receive so GRO works
transparently — no driver-side TSO).
- COE checksum offload bits (TSO_COE_CTRL register).
- EEE / autoEEE (separate vendor sub-directory).
- AVS (adaptive voltage scaling).
- Statistics / ethtool / WoL / coalescing tuning.
- Multicast hash table — driver runs permissive (broadcast + multicast
pass; effectively promiscuous in steady state). Filter tightening
would be a follow-up.
- PM suspend/resume — leaves the IP at HW defaults across suspend.
Verified clean compile under `make W=1` against Linux 7.0, ARM target,
OpenIPC toolchain. Real-hardware verification is gated on the
hi3516av100_neo firmware-side bring-up (separate openipc/firmware
PR), which uses this driver and validates QEMU smoke + login + ping.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This was referenced May 22, 2026
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Summary
Adds mainline support for the Hi3516AV100 / Hi3516DV100 V2A SoC family (Cortex-A7, ARMv7) — same shape as #43 was for the V2 cv200 family, but ARMv7 with GIC + arch-timer instead of VIC + SP804, and a new GMAC ethernet driver (vendor's higmac IP).
Adds
Commit 1 — SoC core (CRG + DT + Kconfig):
drivers/clk/hisilicon/crg-hi3516av100.c(~330 lines): ported from vendor 4.9 BSPclk-hi3516a.conto the modern crg- platform_driver scaffold (mirroringcrg-hi3516cv200.c). 34 fixed-rate roots, APLL stub at 850 MHz, 9 muxes, 1 fixed-factor (clk_sysapb = sysaxi_mux / 4), 15 gates,CLK_OF_DECLAREearly init for sysctrl timer slots + early UART/ETH consumers.arch/arm/boot/dts/hisilicon/hi3516av100.dtsi(~290 lines): GIC v2, arch timer, PL011 uart0-3, PL022 spi0/1, PL061 gpio0-3, hisi-i2c-hisilicon, hisi-spi-nor, higmac at 0x10090000 with embedded mdio sub-node, himci mmc0/1.arch/arm/boot/dts/hisilicon/hi3516av100-demb.dts: reference board (1 GiB RAM, single Cortex-A7 Linux CPU per vendor BSP layout, UART0 console, higmac + PHY).include/dt-bindings/clock/hi3516av100-clock.h: clock IDs.arch/arm/mach-hibvt/Kconfig:ARCH_HI3516AV100(selects ARM_GIC + HAVE_ARM_ARCH_TIMER + COMMON_CLK_HI3516AV100).drivers/clk/hisilicon/Kconfig+ Makefile,arch/arm/boot/dts/hisilicon/Makefile.Commit 2 — higmac ethernet driver:
drivers/net/ethernet/hisilicon/hisi_higmac.c(~990 lines): minimal mainline driver for the higmac (Gigabit Ethernet MAC) IP. Vendor 4.9 BSP carries a 3000-line driver with TSO, EEE, AVS, multicast filters, statistics, ethtool, PM; this port strips everything except the descriptor-ring TX/RX path that QEMU emulates and that real hardware needs to boot. Sufficient for ifup, DHCP, and ping. Production features can be layered on later.hw/net/hisi-gmac.c) which mirrors the vendor IP.Verification
Out of scope (follow-ups)
Test plan
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