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resolved Conflicts:
It is ready for basic hardware testing, but not production-complete. Region filtering, permanent policy locking, and board-level external-mux GPIO switching/delay still need implementation.
Spimonitor is not monitoring the traffic from spi controller. Spi monitor is only monitoring the traffic from either BMC or host.
…9 for pulse helper. and split it into explicit assert/release operations so monitor setup happens while the BMC is held in reset.
BMC master and Host. Configure board-level GPIO: - BMC: mux select bit 0, active-low OE bit 1, reset bit 7 - Host: mux select bit 2, active-low OE bit 3, reset bit 6 Switch the shared SPIM1/2 BMC mux from RoT value 1 to BMC value 0.
…orks for spi2@0 and spi2@1.
Adding a PROT recovery timeout: if BMC CSIN stays low, assert BMC reset, route to RoT, reset flashes and monitors, then retry
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This pull request includes:
Added SPI2 read tests.
Completed the SPI Monitor implementation.
Tested SPIM1–SPIM4 with both the BMC and CPU master controllers.