Swmbx i2c#308
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The previous PFR mailbox bringup split the read path across an IPC boundary: the i2c server-runtime drained the slave RX, woke the client, and the client (owning SwmbxCtrl) answered master reads over IPC. The round-trip never completed inside the AST controller's TX clock-stretch window, so the master sampled an idle bus (0xff) and FIFO / back-to-back reads failed. Move SwmbxCtrl into the server process and serve reads inline in the slave IRQ, mirroring aspeed-rust's in-ISR swmbx_target callback model: - server_main now owns SwmbxCtrl, configures PROTECT/NOTIFY/FIFO policy and per-port protection bitmaps, and answers get_msg + write_slave response before releasing the controller's TX stretch. No logging on the hot path between offset receipt and the TX-DMA arm. - pfr_i2c_notify_client is retired to an idle placeholder; the system image layout is unchanged. HAL / driver changes that make synchronous serving correct: - Add SlaveWrRecvdStop (HAL) / DataReceivedStop (peripheral) so a write burst that latches data and STOP in one status is delivered as one event and the transaction is finalized in place. - Stop setting AST_I2CC_SLAVE_PKT_SAVE_ADDR: the matched address is no longer prepended to RX, restoring plain offset-addressed SMBus [offset, data...] semantics. RX length and copy paths skip the addr byte only when the bit is set. - Normalize slave status (mask address-indicate / pending / NAK bits), surface the inactive-timeout as a Stop so the per-transaction cursor resets, and arm slave TX via TX_DMA_EN with a DMA actual-length reset to avoid clocking out stale 0xff. - server-runtime: replace the single-slot RX latch with a depth-4 event ring so a DataReceived/Stop burst is not split across wake-ups. SwmbxCtrl: zero the (uninitialized device-memory) backing region on init, add take_notify() to drain latched node notifications, and return 0 from get_msg on an empty FIFO instead of FifoEmpty. system.json5: move the server to Bus 0 (I2C0 @ 0x7e7b0080, IRQ 110), map the swmbx_buf SRAM region, and right-size the per-app flash. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
- Add FIFO_QUEUE_SLOTS = SWMBX_FIFO_DEPTH + 1: heapless spsc::Queue<T,N> stores at most N-1 elements, so a FIFO at max depth was one slot short. - Remove msg_index: dead manual cursor shadowing the queue's own head/tail. - Fix enable_behavior validation: reject flag == 0 and unknown bits; prior check accepted KNOWN | UNKNOWN combinations silently. - Gate FIFO overflow notify on SWMBX_NOTIFY (global + per-node) and latch on the FIFO's bound address, not the caller's running cursor. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
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