Reverted ULONG to be 4 bytes long, fixing missaligment issue in the current port

[cpdpls]

This PR should fix #520. After the recent internal meeting, here is the solution we came up with. The riscv64 port now follows the same type size as other 64-bit architectures in tx_port.h. This also fixes some misalignment issues reported in #520.

This also makes other ThreadX components such as NetX working again (ULONG was assumed to be 4 bytes and not 8 bytes as the current official port).

PR checklist

• Updated function header with a short description and version number
• Added test case for bug fix or new feature
• Validated on real hardware (Microchip Polarfire SOC -- riscv64-unknown-elf-gcc (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 8.3.0 and (Qemu Risc-V64 emulator 11.0 )

[fdesbiens]

@akifejaz Please review.

[akifejaz]

@akifejaz Please review.

Sure, I'll review shortly.

Hi @cpdpls, there is PR which enables regression for risc-v ports. It has bunch of tests that runs on both RV32 and RV64. It would be nice if you can try running those.

here is how you can run tests..

cd ~/threadx
./scripts/build_tx_riscv.sh 
./scripts/test_tx_riscv.sh

you would need to merge the upstream/dev branch into yours before running tests.

[cpdpls]

Hi @akifejaz

That was literally the question I was about to ask, so your comment comes in super handy ! I'll surely run the test. Thank you for your input !