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1. Open-Source-ASIC-Design-RTL-to-GDSII Open-Source-ASIC-Design-RTL-to-GDSII Public

   Hands-on open-source ASIC design portfolio documenting the complete RTL-to-GDSII flow, SoC verification, and gate-level simulation using OpenLane, OpenROAD, SKY130, Caravel, and VSDSquadron.

   Verilog 1